1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same. More particularly, the present invention relates to a split gate type flash memory device and a related method for manufacture.
2. Description of the Related Art
Electrically erasable and programmable nonvolatile semiconductor memory devices are a popular choice for many modern electronic devices, including mobile communication systems, memory cards and the like. For example, Electrically-Erasable Programmable Read Only Memory (EEPROM) is commonly used to store data in cellular phones and in digital camera memory cards. Flash memory, which is a type of EEPROM, may be programmed one cell at a time, but erased in block or sector units comprising multiple memory cells. Flash memory devices typically include one transistor having a floating gate and another transistor having an electron trap layer. Examples of transistors having a floating gate include stacked gate transistors, split gate transistors, and the like.
FIG. 1A is a schematic showing a planar view of a conventional flash memory device having a split gate transistor (referred to hereafter as “split gate type flash memory device”). FIG. 1B is a schematic showing a cross-sectional view taken along a line between X and X′ in FIG. 1A. FIG. 1B shows a pair of memory cells.
Referring to FIGS. 1A and 1B, a semiconductor substrate 10 has an active region 11 defined by a device isolation region 13. Device isolation region 13 typically comprises a shallow trench isolation (STI) film. In addition, the split gate type flash memory device has a source region 15 formed in semiconductor substrate 10. Source region 15 is formed in a predetermined portion of active region 11. Source region 15 is a common source for the pair of memory cells shown in FIG. 1B. Source region 15 is extended in length together with a horizontally adjacent source region 15 to form a common source line.
A pair of floating gates 20 is formed on semiconductor substrate 10 adjacent to both sides of source region 15. Each floating gate 20 has an upper surface covered by an inter-gate insulating film 25. At least one sidewall of floating gate 20 is covered by a control gate 30. Control gate 30 extends from the sidewall of floating gate 20 to cover the upper surface of inter-gate insulating film 25, and to cover a portion of semiconductor substrate 10 disposed adjacent to floating gate 20 and on the distal sides of floating gate 20 relative to source region 15. Control gate 30 extends horizontally to be parallel with the common source line. The horizontally extended control gate 30 functions as a word line.
A drain region 35 is formed in semiconductor substrate 10 adjacent to each control gate 30. A portion of each drain region 35 is typically overlapped by control gates 30. Each drain region 35 is connected with a bit line (not shown) through a contact. A coupling insulating film 40 is formed between each floating gate 20 and semiconductor substrate 10. Coupling insulating film 40 extends down each floating gate 20 and is overlapped, at least in part, by a tunneling insulating film 45 extending over the sidewall of floating gate 20 covered by control gates 30. Tunneling insulating film 45 is patterned according to the shape of control gate 30. Coupling insulating film 40 and tunneling insulating film 45, both of which are formed below control gates 30, function collectively as a gate insulating film for the resulting MOS transistor.
The split gate type flash memory device typically further includes spacers 50 formed on sidewalls of control gate 30, on a sidewall of each floating gate 20 and on a proximal portion of inter-gate insulating film 25 relative to source region 15. Spacers 50 are not essential structural elements, but are typically formed in cases where flash memory devices are merged with the logic devices.
The split gate type flash memory device has a structure wherein each floating gate 20 is isolated from a respective control gate 30. As such, floating gate 20 is electrically insulated. The split gate type flash memory device stores data using various techniques that manipulate cell current, such as electron injection (programming) and electron emission (erasing).
In a case where a programming operation is performed with respect to only a single selected cell, a high voltage, e.g., more than 9V, is typically applied to source region 15, and an appropriate voltage (VD1) such as 0V is applied to drain region 35. Additionally, a voltage at least as high as a threshold voltage (VG1) is applied to control gate 30 of the selected cell, and a voltage of 0V is applied to control gate 30 of the non-selected cell. In this case, hot electrons are injected into floating gate 20 through coupling insulating film 40 in semiconductor substrate 10 down floating gate 20 adjacent to control gate 30 in the selected cell. However, this result does not occur in the non-selected cell.
Unfortunately, the split gate type flash memory device suffers from a problem related to the programming operation. The problem, known as the “disturbance problem”, is experienced in the non-selected cell during programming of the selected cell. The disturbance problem is caused, at least in part, by the high voltage applied to source region 15 during programming and more particularly to the portion of source region 15 overlapped by floating gate 20. To be more specific, even though the threshold voltage is not applied to the control gate 30 of the non-selected cell, a depletion area extends toward both sides of source region 15 as a result of the high voltage applied to source region 15. Furthermore, there is an effect in which a certain voltage appears to be applied to floating gate 20 in the non-selected cell. As a result, the depletion area extends through semiconductor substrate 10 down a channel region in the non-selected cell and generates a punch-through, thereby causing the non-selected cell to be programmed together with the selected cell.